For proper operation of certain types of systems, it is important that all the loads on the board receive the clock signal at essentially the same time often such systems are manufactured using integrated circuit chips on a printed circuit board. Because the distance from the clock generating circuit to the different chips is not the same, unless a clock synchronizing technique is used, the loads will receive the clock signal at different times. Various techniques have been used in the prior art to synchronize the clock signal so that it is received by all the loads at the same time. These prior art techniques include designing the printed circuit board so that all the lines between the clock signal and the loads are the same length. In order to achieve synchronization, some of the lines carrying the clock signal may have complex serpentine paths to achieve a longer delay. Another technique uses a clock generator with programmable clock edges. Both of these well known techniques require knowledge about the physical construction of the printed circuit board beforehand and require the system designer to calculate differences in transit times for the clock signals.
A clock generator circuit taught in U.S. Pat. No. 5,298,866 is illustrated in FIG. 1. A clock input signal line 1 is coupled to a first end of a maximum delay line 2. A second end of the maximum delay line 2 is coupled to a phase detector 3 for comparing the timing between two signals. This phase detector is similar to a phase-frequency detector as used in phase-locked-loops. An output of the phase detector 3 is coupled to a low-pass filter 4 for filtering the output of the phase detector. The variable delay lines 5 and 6 are matched so that they have equal delays. Both variable delay lines 5 and 6 are coupled to and controlled by the output of the low-pass filter 4. The maximum delay of the variable delay lines 5 and 6 is equal to half of the delay of the maximum delay line 2. The variable delay lines 5 and 6 will typically be implemented as voltage controlled delay lines.
An output of the variable delay line 5 is coupled as the other input to the phase detector 3. The clock input signal line 1 is coupled as the input of the variable delay line 6. The output of the variable delay line 6 is coupled to an input of an output buffer 7. The output buffer 7 is typically implemented as a TTL or CMOS low impedance driver. An output of the output buffer 7 is coupled by a drive transmission line 11 to a load 9. A sense transmission line 10 is also coupled to the load 9 and to an input of an input buffer 8. An output of the input buffer 8 is coupled as the input to a variable delay line 5. The input buffer 8 can be implemented as a typical TTL or CMOS input gate. The resistors R1 and R2 are termination resistors used to prevent reflections on the transmission lines, and are normally external to the integrated circuit because of their power dissipation. The drive 11 and sense 10 transmission lines are required to have equal propagation delays, achieved by matching the length of these lines. To ensure this, the lines are formed parallel to one another on the printed circuit board so that they essentially have identical paths.
The clock input signal line 1 is applied to a plurality of identical clock driver sections, each driving a different load 9 with a different external propagation delay along drive and sense transmission lines 11 and 10. Within each clock driver section, the clock input signal line 1 is applied to a fixed maximum delay line 2 and a variable delay line 6. The output of the variable delay line 6 is buffered by the output buffer 7 and applied to the drive transmission line 11 and then to the load 9. The drive transmission line 11 has a propagation time delay t.sub.d. This signal then returns to the clock driver section through the sense transmission line 10. The sense transmission line 10 also has a propagation time delay t.sub.d, which makes the roundtrip delay from the clock driver section to the load 9 and back again, a time of 2t.sub.d. The sense transmission line 10 is terminated at the sense point 14 between the two resistors R1 and R2.
The sense point 14 is coupled to the input of the input buffer 8. The output of the input buffer 8 is applied to the variable delay line 5. The other end of the variable delay line 5 is input into the phase detector 3 where it is compared with the output of the maximum delay line 2. The output of the phase detector 3 is then filtered by the low-pass filter 4 and applied to control the variable delay lines 5 and 6 with the control signal line 12. The control signal line 12 is used to vary the delay of the variable delays 5 and 6 such that the inputs to the phase detector 3 arrive simultaneously. The phase detector 3, low pass filter 4 and the voltage controlled variable delay lines 5 and 6 form a Delay Locked Loop.
If the loop gain is sufficient, the delay from the clock input signal 1 through the variable delay line 6, the output buffer 7, the drive transmission line 11, the sense transmission line 10, the input buffer 8 and the variable delay line 5 will be driven by the closed loop, to be equivalent to the delay through the maximum delay line 2. The sufficient gain needed for this delay can be achieved by using an integrator in the low pass filter 4. Any variation in the propagation time delay t.sub.d will automatically be compensated for by the closed loop so that the total delay from the clock input signal 1 to the output 13 of the variable delay line 5 will always be the same, as long as the required delay correction does not exceed the limits of the ranges of the variable delay lines 5 and 6. This relationship can be expressed by the following equation: EQU Delay(A)=Delay(E)+Delay(G)+Delay(F)+Delay(D)+2t.sub.d. (1)
Since the variable delay lines 5 and 6 are identical, EQU Delay(E)=Delay(D). (2)
The delays through the maximum delay line 2, the output buffer 7 and the input buffer 8 are all constants. Equation (1) can then be rewritten as EQU t.sub.d +Delay(E)=[Delay(A)-Delay(F)-Delay(G]/2 (3)
or EQU t.sub.d +Delay(E)=constant. (4)
If the same clock input signal 1 is applied to a number of identical deskew elements driving loads at different distances, with different transmission line delays, t.sub.d, Equation (4) shows that the clock edge will arrive at all loads driven by the different deskew elements at the same time, assuming that the constant is the same for all of the deskew elements in the circuit. As can be seen, the time delay t.sub.d for the longest correctable load will be equal to the constant, with the variable delay time Delay(E) for this load set at zero. For those loads whose time delay t.sub.d is not as long the constant, then the difference will be made up by adjusting the variable delay time Delay(E) for that load, so that all loads will receive the clock signal input simultaneously. Thus, the delay time Delay(E) through the variable delay lines 5 and 6 for each load will equal the time delay t.sub.d for the load with the longest transmission lines minus the time delay t.sub.d for the specific load or EQU Delay(E)=constant-t.sub.d ( 5)
The external transmission line section of FIG. 1 is illustrated in FIG. 2. This external transmission line section requires two transmission line segments 10 and 11, one for driving the load 9 and one for sensing the round trip delay from the load 9. The two transmission line segments 10 and 11 can be considered a single tapped transmission line with a tap in the middle to accommodate the load 9.
To prevent reflections from occurring along the transmission line, a resistive termination is included at the sense end 14 of the transmission line. This resistive termination at the output is comprised of the network including the two resistors R1 and R2. The node between the two resistors is the sense node 14 as discussed above. If the transmission line is not properly terminated, reflections from the sense node 14 of the line will be reflected back towards the load 9 and cause undesirable distortion or ringing to appear at the load 9. Were such reflections to reach the output buffer 7 or driver they would be again reflected, further compounding the problem.
The transmission lines 10 and 11 each have a characteristic impedance which is equivalent and designated as Z.sub.o. This characteristic impedance will typically have a value of 50 ohms, but can also have other impedance values depending on the transmission lines. The termination network comprising the resistors R1 and R2 is resistive in nature and has an equivalent Thevenin value equal to the characteristic impedance Z.sub.o of the transmission line. This type of termination is commonly known as Thevenin termination. It will be apparent to one of ordinary skill in the art that a purely resistive Thevenin termination network can have significant static power dissipation for TTL and CMOS levels.
In reality, no load will have a negligible impedance. A typical load used in common circuitry is a CMOS input buffer which is primarily capacitive and in the range of 5 to 20 picofarads. Capacitors of this size on a tapped delay line will cause reflections of the drive signal which will be reflected back towards the driver or output buffer 7. This reflection will be reflected back by the driver 7 and cause distortion at the load 9 which can be significant with fast rise and fall time signals. Compromise termination and the use of non-linear, TTL type, drivers can help this problem, but will not eliminate it.
What is needed is an apparatus for deskewing clocks without requiring the system designer to calculate transit times along transmission lines or the overhead associated with parallel traces. Further what is needed is a way to terminate the transmission line without the significant static power dissipation of a parallel termination. What is also needed is a way to eliminate the reflection and re-reflection on the transmission line which causes distortion at the load 9.